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cy8cmbr2044 four button capsense ? controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-57451 rev. *e revised may 22, 2012 four button capsense ? controller features easy to use capaciti ve button controller ? four-button solution configurable through hardware straps ? no software tools or programming required ? four general-purpose outputs (gpos) ? gpos linked to capsense ? buttons ? gpos support direct led drive robust noise performance ? specifically designed for superi or noise immunity to external radiated and conducted noise ? low radiated noise emission smartsense? auto-tuning ? saves time and effort in device tuning ? capsense parameters dynamically set in runtime ? maintains optimal button performance even in noisy environment ? wide parasitic capacitance c p range (5 pf?40 pf) system diagnostics of capsense buttons - reports any faults at device power up ? button shorted to ground ? button shorted to v dd ? button to button short ? improper value of modulator capacitor (c mod ) ? parasitic capacitance (c p ) out of range advanced features ? toggle on/off feature on gpos ? flanking sensor suppression (fss) provides robust sensing even with closely spaced buttons ? configurable led on time after button release ? button output reset if touched for excessive time ? user-controlled button scan rate ? serial debug data output ? simplifies production lin e testing and system debug wide operating voltage range ? 1.71 v to 5.5 v ? ideal for both regulated and unregulated battery applications low power consumption ? supply current in run mode as low as 15 a [1] per button ? deep sleep current: 100 na industrial temperature range: ?40 c to + 85 c 16-pad quad flat no leads (qfn) package (3 mm 3 mm 0.6 mm) overview the cy8cmbr2044 incorporates several innovative features to save time and money to quickly enable a capacitive touch sensing user interface in your design. it is a hardware configurable device and does not require any software tools or coding. this device is enabled with cypress's revolutionary smartsense? auto-tuning algorithm. smartsense? auto-tuning ends the need to manually tune the user interface during development and production ramp. this speeds the time to volume and saves valuable engineering time, test time and production yield loss. the cy8cmbr2044 capsense controller supports up to four capacitive touch sensing buttons and four general purpose outputs (gpos). the gpo is an active low output controlled directly by the capsense input making it ideal for a wide variety of consumer, industrial, and medical applications. the wide operating range of 1.71 v to 5. 5 v enables unregulated battery operation, further saving compone nt cost. also, the same device can be used in different applications with different power supplies, including low power supplies. this device supports ultra low-power consumption in both run mode and deep sleep mode to stretch battery life. in addition, this device also supports many advanced features which enhance the robustness and user interface of the end solution. some of the key advanced features include noise immunity and fss. noise immunity improves the immunity of the device against radiated and conducted noise, such as audio and radio frequency (rf) noise. fss prov ides robust sensing even with closely spaced buttons. fss is a critical requirement in small form factor applications. serial debug data output gives t he critical information about the design, such as button cp and signal-to-noise ratio (snr). this further helps in production line testing. note 1. power consumption calculated with 1.7% touch time, 500 ms scan rate, and c p of each sensor < 19 pf.
cy8cmbr2044 document number: 001-57451 rev. *e page 2 of 29 contents pinout ................................................................................ 3 typical circuits ................................................................. 4 schematic 1: 4-buttons, 4-leds with auto reset enabled .................................................... 4 schematic 2: 3-buttons, 3-leds, 2-outputs to master, and advanced features enabled ..... 5 configuring the cy8cmbr2044 . .............. .............. ......... 6 device features ................................................................ 6 capsense buttons ...................................................... 6 smartsense auto tuning ............................................ 6 general purpose outputs ............................................ 6 toggle on/off ........................................................... 7 flanking sensor suppression (fss) ........................... 7 led on time .............................................................. 7 button auto reset ............... ........................................ 8 system diagnostics ..................................................... 9 serial debug data ............... ...................................... 10 power consumption and device operating modes .................................................. 12 additional components to enable advanced features .. ........................................ 14 response time ........ .............. .............. .............. ....... 14 layout guidelines and best practices ......................... 15 capsense button shapes ......................................... 16 button layout design ................................................ 16 recommended via hole placement ......................... 16 example pcb layout design with four capsense buttons and four leds ................... 17 electrical specifications ................................................ 18 absolute maximum ratings ... .................................... 18 operating temperature ............................................. 18 dc electrical characteristics ..................................... 19 ac electrical specifications ....................................... 21 capsense specifications .......................................... 21 ordering information ...................................................... 22 ordering code definitions ..... .................................... 22 package diagram ............................................................ 23 package information ................................................. 23 appendix ......................................................................... 24 acronyms ........................................................................ 26 document conventions ................................................. 26 units of measure ....................................................... 26 document history page ................................................. 27 sales, solutions, and legal information ...................... 29 worldwide sales and design s upport ......... .............. 29 products .................................................................... 29 psoc solutions ......................................................... 29
cy8cmbr2044 document number: 001-57451 rev. *e page 3 of 29 pinout table 1. pin diagram and definitions ? cy8cmbr2044 pin label type [2] description if unused 1 gpo1 do gpo activated by cs1 leave open 2 gpo0 do gpo activated by cs0 leave open 3 toggle/ fss ai controls fss and toggle on/off features ground 4 delay ai controls led on time. for details refer to table 2 on page 6 ground 5 cs0 aio capsense input, controls gpo0 or serial debug data out ground 6 cs1 aio capsense input, controls gpo1 or serial debug data out ground 7v ss pground 8 cs2 aio capsense input, controls gpo2 or serial debug data out ground 9 arst aido controls button auto reset leave open 10 cs3 aio capsense input, controls gpo3 or serial debug data out ground 11 xres di device reset, active high, with internal pull down leave open 12 scanrate / sleep ai controls scan rate and deep sleep ground 13 v dd p power 14 gpo3 do gpo activated by cs3 leave open 15 c mod ai external modulator capacitor, connect a 2.2 nf (10%) to ground 16 gpo2 do gpo activated by cs2 leave open qfn (top view) gpo1 toggle/fss delay cs0 1 2 3 4 11 10 9 16 15 14 13 cmod gpo3 v dd scanrate/sleep cs1 cs2 arst gpo0 cs3 xres gpo2 v ss 12 5 6 7 8 note 2. ai ? analog input, aio ? analog input / output, aido ? analog input / digital output, di ? digital input, do ? digital output , p ? power
cy8cmbr2044 document number: 001-57451 rev. *e page 4 of 29 typical circuits schematic 1: 4-buttons, 4-leds with auto reset enabled in the above schematic, the device is configured to support: cs0?cs3 pins: 560- ? to capsense button ? four capsense buttons (cs0?cs3) gpo0?gpo3 pins: led and 560- ? to v dd ? capsense buttons driving 4 leds (gpo0?gpo3) c mod pin: 2.2 nf to ground ? modulator capacitor xres pin: floating ? for external reset toggle/fss pin: ground ? toggle on/off disabled ? fss disabled arst pin: 5 k ? to ground ? button auto reset enabled, 20 second time delay pin: ground ? led on time disabled scanrate/sleep pin: ground ? user configured scan rate = 20 ms to enable serial debug data output, connect a 5.6 k ? resistor on r9 or r12. ? vdd led 2 d4 led r4 560 e led3 d3 led r3 560 e vdd c1 10uf cs3 cs0 1 r 7 560 e cs1 r8 560e cs1 1 vdd vdd r12 0e tp2 cs2 xr e s vdd c3 0. 1uf led 1 d1 led led 0 r 1 560 e d2 led r 2 560 e vdd u5 cy8cmbr2044 gpo1 1 gpo0 2 tog gle /f ss 3 delay 4 cs0 5 cs1 6 vss 7 cs2 8 arst 9 cs3 10 xr e s 11 scanrate/ sleep 12 vdd 13 gpo3 14 cm od 15 gpo2 16 c2 2.2n f r9 0e cs0 r 6 5 k(10% ) r 10 560e cs2 1 r1 1 560e cs3 1 tp1 arst
cy8cmbr2044 document number: 001-57451 rev. *e page 5 of 29 schematic 2: 3-buttons, 3-leds, 2-outputs to master, and advanced features enabled in the above schematic the device is configured to support: cs0?cs2 pins: 560- ? to capsense buttons; cs3 pin: ground ? three capsense buttons (cs0?cs2) ? cs3 not used in design gpo0?gpo2 pins: led and 560- ? to vdd; gpo3 floating; gpo0?gpo1 pins interfaced to master ? capsense buttons driving 3 leds (gpo0?gpo2) ? gpo0, gpo1 interfaced to mast er for direct status read c mod pin: 2.2 nf to ground ? modulator capacitor xres pin: floating ? for external reset toggle/fss pin: 5.1 k ? to ground ? toggle on/off disabled ? fss enabled arst pin: 5 k ? to ground ? button auto reset enabled, auto reset period = 20 seconds delay pin: 4 k ? to ground ? led on time of 1000 ms scanrate/sleep pin: 560 ? to master ? user configured scan rate = 30 ms ? master to control device operating mode to enable serial debug data output, connect a 5.6 k ? resistor on r11. ? r 9 560e vdd vd d xr es led0 led1 c2 2.2nf gpo3 arst r6 5k(10%) r4 5.1k(5%) d3 led r10 560e led2 r5 4k(1% ) vd d r11 0e r2 560e(1% ) scan to master to master to master u5 c y 8cmbr2044 gpo1 1 gpo0 2 tog gle/ fss 3 delay 4 cs0 5 cs1 6 vs s 7 cs2 8 arst 9 cs3 10 xre s 11 scanrate/ sleep 12 vdd 13 gp o 3 14 cm od 15 gpo2 16 d1 led r1 560e d2 led vdd r3 560e tp1 vdd c3 0. 1uf vd d c1 10uf cs0 cs0 1 r7 560e cs1 r8 560e cs1 1 cs2 1 cs2
cy8cmbr2044 document number: 001-57451 rev. *e page 6 of 29 configuring th e cy8cmbr2044 the cy8cmbr2044 device features are configured using external resistors. the resistors on the hardware configurable pins are determined by the device upon power-on. the appendix gives the matrix of features enabled using different external resistor configurations. to know more about the required settings for your design, refer to the cy8cmbr2044 design guide . device features capsense buttons device supports up to four capsense buttons ground the csx pin to disable capsense input a 2.2-nf (+ 10%) capacitor must be connected on the c mod pin for proper capsense operation the parasitic capacitance (c p ) of each button must be less than 40 pf for proper capsense operation smartsense auto tuning device supports auto tuning of capsense parameters no manual tuning required; all parameters are automatically tuned by the device compensates printed circuit board (pcb) variations, device process variations, and pcb vendor changes ensures portability of the user interface design general purpose outputs the gpox is controlled by the corresponding csx gpox pin outputs are in strong drive mode [3] active low output ? support s sinking configuration if csx is disabled (grounded), then the corresponding gpox must be left floating a 5-ms pulse is sent after 175 ms after device power-up, on a gpox, if the csx fails the system diagnostics. table 2. advanced features supported by cy8cmbr2044 feature benefits toggle on/off button retains state on touch (on/off) flanking sensor suppression (fss) helps in distinguishing closely spaced buttons led on time gives an led effect on button release button auto reset disables false output trigger due to conducting object placed close to button system diagnostics support for production testing and debugging serial debug data support for production testing and validating design low power sleep mode and deep sleep mode low power consumption note 3. when a pin in in strong drive mode, it is pulled up to v dd when the output is high and pulled down to ground when the output is low. the output cannot be floating.
cy8cmbr2044 document number: 001-57451 rev. *e page 7 of 29 toggle on/off toggles the gpo state at each button touch. used for mechanical button re placement. for example, wall switch. flanking sensor suppression (fss) helps to distinguish closely spaced buttons. also used in situations when a button can produce opposite effects. for example, an inte rface with two buttons for brightness control (up or down). fss action can be explained for the following different scenarios: ? when only one button is touched, it is reported as on. ? when more than one button is detected as on and previously one of those buttons was touched, then the previously touched button is reported as on. led on time provides better visual feedba ck when a button is released and improves the design?s aesthetic value. the gpox is driven low for a spec ified interval after the corre- sponding csx button is released. when a button gets reset, led on time is not applied on the corresponding gpo. in figure 3 on page 7 , gpo0 goes high prematurely (prior to led on time) because cs1 button is released. therefore, the led on time counter is reset. now, gpo1 remains low for led on time after releasing cs1. led on time can range from 0?2000 ms. led on time resolution is 20 ms. figure 1. example of toggle feature on gp0 figure 2. button status with respect to finger touch when fss is enabled figure 3. example led on timing diagram on gpo0 ? cs0 gpo0 led ? on ? time
cy8cmbr2044 document number: 001-57451 rev. *e page 8 of 29 figure 4. example led on timing diagram on multiple gpo0 and gpo1 button auto reset prevents button stuck, due to metal object placed close to a button. useful when gpo output to be kept on only for a specific time. if enabled, the gpox is driven for a maximum of button auto reset period when csx is continuously touched. see figure 5 on page 8 . button auto reset period can be set to 5 or 20 seconds. after the button auto reset has been triggered, the csx hold time of that button after the button has been released is given in table 3 . the hardware configuration is shown in ta b l e 1 5 in appendix . figure 5. example of button auto reset on gp0 cs0 gpo0 cs1 gpo1 start ? led ? on ? time ? counter restart ? led ? on ? time ? counter reset ? led ? on ? time ? counter led ? on ? time table 3. button hold time after auto reset button press time after button auto reset button hold time (ms) < 2 sec 220 > 2 sec scanrate + 200 cs0 gpo0 auto ? reset ? period gpo0 ? is ? not ? driven ? after ? auto ? reset ? period button ? is ? touched ? for ? more ? than ? the ? auto ? reset ? period
cy8cmbr2044 document number: 001-57451 rev. *e page 9 of 29 system diagnostics a built-in power-on self test (post) mechanism performs some tests at power-on reset (por), which can be useful in production testing. if any button fails these tests, a 5 ms pulse is sent out on the corresponding gpo withing 175 ms after por. following tests are performed on all the buttons - button shorted to ground if any button is found to be shorted to ground, it is disabled. see figure 6 . figure 6. button shorted to ground button shorted to v dd if any button is found to be shorted to v dd , it is disbled. see figure 7 . figure 7. button shorted to vdd button to button short if two or more buttons are found to be shorted to each other, all of these buttons are disabled. see figure 8 . figure 8. butto n to button short improper value of c mod recommended value of c mod is 2 nf to 2.4 nf. if the value of c mod is found to be less than 1 nf or greater than 4 nf, all the buttons are disabled. button c p > 40 pf if the parasitic capacitance (c p ) of any button is found to be more than 40 pf, that button is disabled.
cy8cmbr2044 document number: 001-57451 rev. *e page 10 of 29 figure 9. example showing cs0 and cs1 passing the post and cs2 and cs3 failing in figure 9 , cs0 and cs1 buttons are enabled; cs2 and cs3 buttons are disabled because they failed the power-on self test. a 5 ms pulse is observed on gpo2 and gpo3. serial debug data used to see capsense data for debug purposes if enabled, debug data is transmitted using uart communication protocol. to enable this feature pull down any one of the capsense pins with a 5.6 k ? resistor to ground. data is sent out on the same capsense pin if more than one capsense pin is pulled down, debug data is sent out only on one capsense pin and the priority is cs0 > cs1 > cs2 > cs3 the cypress multichart tool can be used to view the data as a graph. serial data is sent out with ~115,200 baud rate firmware revision, capsense st atus, gpo status, raw count, baseline, difference count, and parasitic capacitance of all sensors are sent out for designs having a maximum of three capsense buttons, cypress recommends to take the debug data on a capsense button that is not used in design for designs with four capsense buttons, cypress recommends taking debug data on two capsense buttons. for example, pull down cs0 with a 5.6 k ?? resistor and read data of cs1, cs2, and cs3. next, pull down cs1 with a 5.6 k ? resistor and read data of cs0, cs2, and cs3 for more information on raw count, baseline, difference count and parasitic capacitance, refer to getting started with capsense , section 2. for more information on multichart tool, refer to an2397 capsense data viewing tools, method 2. multichart tool arranges the data in the format as shown in table 4 . the serial debug data is sent by the device in the order as per table 5 . max time to get 5 ms pulse is 175 ms after power up 5 ms pulse table 4. serial debug data arranged in multichart s.no. raw count array baseline array signal array msb lsb msb lsb msb lsb 0 0x00 fw_revision cs _status gpo_status 0x00 cs2_c p 1 0x00 cs0_ c p 0x00 cs1_c p 0x00 cs3_ c p 2 cs0_rawcount cs0_baseline cs0_diffcount 3 cs1_rawcount cs1_baseline cs1_diffcount 4 cs2_rawcount cs2_baseline cs2_diffcount 5 cs3_rawcount cs3_baseline cs3_diffcount
cy8cmbr2044 document number: 001-57451 rev. *e page 11 of 29 table 5. serial data output sent by cy8cmbr2044 byte data notes 0 0x0d dummy data for multi chart 1 0x0a 20x00? 3 fw_revision ? 40x00? 5cs0_c p cs0 parasitic capacitance in hex 6 cs0_rawcount_msb unsigned 16-bit integer 7 cs0_rawcount_lsb ? 8 cs1_rawcount_msb unsigned 16-bit integer 9 cs1_rawcount_lsb ? 10 cs2_rawcount_msb unsigned 16-bit integer 11 cs2_rawcount_lsb ? 12 cs3_rawcount_msb unsigned 16-bit integer 13 cs3_rawcount_lsb ? 14 cs _status gives capsense button status, l east significant bit (lsb) contains cs0 status 15 gpo_status gives gpo status, lsb contains gpo0 status 16 0x00 ? 17 cs1_c p cs1 parasitic capacitance in hex 18 cs0_ baseline _msb unsigned 16-bit integer 19 cs0_ baseline _lsb ? 20 cs1_ baseline _msb unsigned 16-bit integer 21 cs1_ baseline _lsb ? 22 cs2_ baseline _msb unsigned 16-bit integer 23 cs2_ baseline _lsb ? 24 cs3_ baseline _msb unsigned 16-bit integer 25 cs3_ baseline _lsb ? 26 0x00 ? 27 cs2_c p cs2 parasitic capacitance in hex 28 0x00 ? 29 cs3_c p cs3 parasitic capacitance in hex 30 cs0_ diffcount _msb unsigned 16-bit integer 31 cs0_ diffcount _lsb ? 32 cs1_ diffcount _msb unsigned 16-bit integer 33 cs1_ diffcount _lsb ? 34 cs2_ diffcount _msb unsigned 16-bit integer 35 cs2_ diffcount _lsb ? 36 cs3_ diffcount _msb unsigned 16-bit integer 37 cs3_ diffcount _lsb ? 38 0x00 dummy data for multi chart 39 0xff 40 0xff
cy8cmbr2044 document number: 001-57451 rev. *e page 12 of 29 power consumption and device operating modes the cy8cmbr2044 is designed to meet the low power requirements of battery powered applications. to design for the lowest operating current - ground all unused capsense inputs minimize c p using the design guidelines in getting started with capsense , section 3.7.1. lower the supply voltage. use a higher button scan rate or deep sleep operating mode. to know more about the steps to reduce power consumption, refer to cy8cmbr2044 design guide , section 5. there are two device operating modes: low power sleep mode deep sleep mode low power sleep mode the following flow chart describes the low power sleep mode operation. figure 10. low power sleep mode operation figure 11. low power sleep mode implementation scan all buttons with 20 ms scan rate (scan time + sleep time) no button touched for 2 secs? yes scan all buttons with user defined scan rate. is any button active? yes no no
cy8cmbr2044 document number: 001-57451 rev. *e page 13 of 29 to enable low power sleep mode, the hardware configurable pin scanrate/sleep should be pulled down to ground with resistor ?r? (1%). the scan rate values for different resistor values are given in table 15 in appendix . if the scanrate/sleep pin is pulled to ground without any resistor, the button scan rate is set to 20 ms. the device operates i n low power sleep mode, unless a button is touched. the range of scan rate is 20 to 530 ms. figure 12. average current vs scan rate [4] note 4. number of sensors = 3, cp < 19 pf, 0% touch time, v dd = 3 v.
cy8cmbr2044 document number: 001-57451 rev. *e page 14 of 29 deep sleep mode figure 13. scanrate/sleep pin connection to enable deep sleep mode to enable the deep sleep mode , the hardware configuration pin scanrate/sleep should be connected to the master device as shown in figure 13 . host controller should pull the pin to v dd for the device to go into deep sleep. the host controller output pin should be in strong drive mode, so that the scanrate/sleep pin is not left floating. in deep sleep mode, a ll blocks are turned off and the device current consumption is approximately 0.1 a. there is no capsense scanning in deep sleep mode. scanrate/sleep pin should be pulled low for the device to wake up from deep sleep. when device comes out of deep sleep mode, the capsense system is reinitialized. typical time for reinitialization is 8 ms. any button touch within this time is not reported. after the device comes out of deep sleep, the device operates in low power sleep mode. if the scanrate/sleep pin is pulled high at power on, then the device does not go to deep sleep immediately. the device goes to deep sleep after initializing all internal blocks and scanning all buttons once. if the scanrate/sleep pin is pulled high at power on, then the button scan rate is calculated wh en the device is taken out of deep sleep by the master. additional components to enable advanced features response time response time is the minimum amount of ti me the button should be touched for the de vice to detect as valid button press. cy8cmbr 2044 host external resistor r (controls scan rate) scanrate /sleep digital output pin (controls deep sleep) s.no. feature resistors required notes 1 low power sleep and deep sleep 1 deep sleep is controlled by a master dev ice. when the device comes out of deep sleep, it enters into low power sleep mode ba sed on settings. resistor is not required if both features are not used. 2 toggle/fss 1 to enable both the features only one resist or is required. resistor is not required if both features are not used. 3 delay off 1 resistor is not requ ired if the feature is not used. 4 sensor auto reset 1 resistor is not required if the feature is not used. condition response time (in ms) first button press button scan rate value + 20. for button scan rate value, see ta b l e 1 5 in appendix . consecutive button press after first button press 80
cy8cmbr2044 document number: 001-57451 rev. *e page 15 of 29 layout guidelines and best practices s.no. category min max recommendations / remarks 1 button shape ? ? solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm refer design toolbox 3 button-button spacing equal to button ground clearance ? 8 mm (y dimension in button layout design on page 16 ) 4 button ground clearance 0.5 mm 2 mm refer design toolbox (x dimension in button layout design on page 16 ) 5 ground flood ? top layer ? ? hatched ground 7 mil trace and 45 mil grid (15% filling) 6 ground flood ? bottom layer ? ? hatched ground 7 mil trace and 70 mil grid (10% filling) 7 trace length from button pad to capsense controller pins ? 450 mm refer design toolbox 8 trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9 trace routing ? ? traces should be routed on the non button side. if any non capsense trace crosses capsense trace, ensure that intersection is orthogonal 10 via position for the buttons ? ? via should be placed near the edge of the button to reduce trace length thereby increasing sensitivity 11 via hole size for button traces ? ? 10 mil 12 no. of via on button trace 1 2 1 13 distance of capsense series resistor from button pin ? 10 mm place capsense series resistors close to the device for noise suppression. capsense resistors have highest priority; place them first 14 distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 15 device placement ? ? mount the device on the layer opposite to button. the capsense trace length between the device and buttons should be minimum (see trace length above) 16 placement of components in two layer pcb ? ? top layer ? buttons and bottom layer ? device, other components and traces 17 placement of components in four layer pcb ? ? top layer ? buttons, second layer ? capsense traces and v dd (avoid v dd traces below the buttons), third layer ? hatched ground, bottom layer ? capsense ic or device, other components, and non capsense traces 18 overlay thickness 0 mm 5 mm refer design toolbox 19 overlay material ? ? should be non-conductive material. glass, abs plastic, formica, wood, and so on. there should be no air gap between pcb and overlay. use adhesive to stick the pcb and overlay 20 overlay adhesives ? ? adhesive should be non conductive and dielectrically homogenous. 467mp and 468mp adhesives made by 3m are recommended 21 led back lighting ? ? cut a hole in the button pad and use rear mountable leds. refer to example pcb layout design with four capsense buttons and four leds on page 17 22 board thickness ? ? standard board thickness for capsense fr4 based designs is 1.6 mm.
cy8cmbr2044 document number: 001-57451 rev. *e page 16 of 29 capsense button shapes figure 14. capsense button shapes button layout design figure 15. button layout design x: button to ground clearance (refer to layout guidelines and best practices on page 15 ) y: button to button clearance (refer to layout guidelines and best practices on page 15 ) recommended via hole placement figure 16. recommended via hole placement ?
cy8cmbr2044 document number: 001-57451 rev. *e page 17 of 29 example pcb layout design with four capsense buttons and four leds figure 17. top layer figure 18. bottom layer
cy8cmbr2044 document number: 001-57451 rev. *e page 18 of 29 electrical specifications this section presents the dc and ac electric al specifications of the cy8cmbr2044 device. absolute maximum ratings operating temperature table 6. absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +125 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temper atures above 85 c degrades reliability. v dd supply voltage relative to v ss ?0.5 ? +6.0 v v io dc voltage on capsense inputs and digital output pins v ss ? 0.5 ? v dd + 0.5 v i mig maximum current into any gpo output pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma in accordance with jesd78 standard table 7. operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t j operational die temperature ?40 ? +100 c
cy8cmbr2044 document number: 001-57451 rev. *e page 19 of 29 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 8. dc chip level specifications parameter description min typ max unit notes v dd [5, 6, 7] supply voltage 1.71 ? 5.5 v i dd supply current ? 2.88 4.0 ma conditions are v dd = 3.0 v, t a = 25 c i da active current ? 2.88 4.0 ma conditions are v dd = 3.0 v, t a = 25 c, continuous sensor scan i ds deep sleep current ? 0.1 0.5 a conditions are v dd = 3.0 v, t a = 25 c i av1 average current ? 40 ? a conditions are v dd = 3.0 v, t a = 25 c, 4 ? buttons used, 0% touch time, c p of all sensors < 19 pf and scan rate = 530 ms i av2 average current ? 63 ? a conditions are v dd = 3.0 v, t a = 25 c, 4 ? buttons used, 0% touch time, c p of all sensors > 19 pf and scan rate = 530 ms i av3 average current ? 1 ? ma conditions are v dd = 3.0 v, t a = 25 c, 4 ? buttons used, 100% touch time, c p of all sensors < 19 pf and scan rate = 20 ms i av4 average current ? 1.6 ? ma conditions are v dd = 3.0 v, t a = 25 c, 4 ? buttons used, 100% touch time, c p of all sensors > 19 pf and < 40 pf, scan rate = 20 ms notes 5. when v dd remains in the range from 1.75 v to 1.9 v for more than 50 s, the slew rate when moving from the 1.75 v to 1.9 v range to gre ater than 2 v must be slower than 1 v/500 s. this helps to avoid triggering por. the only other restriction on slew rates for any other voltage rang e or transition is the sr power_up parameter. 6. after power down, ensure that v dd falls below 100 mv before powering backup. 7. for proper capsense block functionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v
cy8cmbr2044 document number: 001-57451 rev. *e page 20 of 29 dc general purpose i/o specifications these tables list guaranteed maximum and minimum specificati ons for the voltage and temperat ure ranges: 3.0 v to 5.5 v and ?40 c < t a < 85c, 2.4 v to 3.0 v and ?40 c < t a < 85 c, or 1.71 v to 2.4 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 9. 3.0 v to 5 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gp0, gp1, gp2, gp3 v dd ? 0.2 ? ? v ioh < 10 a, maximum of 40 a source current in all i/os v oh2 high output voltage on gp0, gp1 v dd ? 0.9 ? ? v ioh = 1 ma, maximum of 2 ma source current in all i/os v oh3 high output voltage on gp2, gp3 v dd ? 0.9 ? ? v ioh = 5 ma, maximum of 10 ma source current in all i/os v ol low output voltage ? ? 0.75 v iol = 25 ma/pin, v dd > 3.30, maximum of 60 ma sink current on gpo0, gpo1, gpo2, gpo3 table 10. 2.4 v to 3.0 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gp0, gp1, gp2, gp3 v dd ? 0.2 ? ? v ioh < 10 a, maximum of 40 a source current in all i/os v oh2 high output voltage on gp0, gp1 v dd ? 0.4 ? ? v ioh = 0.2 ma, ma ximum of 0.4 ma source current in all i/os v oh3 high output voltage on gp2, gp3 v dd ? 0.5 ? ? v ioh = 2 ma, maximum of 4 ma source current in all i/os v ol low output voltage ? ? 0.72 v iol = 10 ma/pin, maximum of 30 ma sink current on gpo0, gpo1, gpo2, gpo3 table 11. 1.71v to 2.4v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gp0,gp1 v dd ? 0.2 ? ? v ioh =10 a, maximum of 20 a source current in all i/os v oh2 high output voltage on gp0,gp1 v dd ? 0.5 ? ? v ioh = 0.5 ma, maximum of 1 ma source current in all i/os v oh3 high output voltage on gp2,gp3 v dd ? 0.2 ? ? v ioh = 100 a, maximum of 200 a source current in all i/os v oh4 high output voltage on gp2,gp3 v dd ? 0.5 ? ? v ioh = 2 ma, maximum of 4 ma source current in all i/os v ol low output voltage ? ? 0.4 v iol = 5 ma/pin, maximum of 20 ma sink current on gpo0, gpo1, gpo2, gpo3
cy8cmbr2044 document number: 001-57451 rev. *e page 21 of 29 ac electrical specifications ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac general purpose i/o specifications capsense specifications parameter description min max unit notes sr power_up power supply slew rate ? 250 v/ms v dd slew rate during power up t xrst external reset pulse width at power up 1 ? ms after supply voltage is valid t xrst2 external reset pulse width after power-up 10 ? s applies after part has booted parameter description min typ max unit notes trise1 rise time on gpo0 and gpo1, cload = 50 pf 15 ? 80 ns v dd = 3.0 to 3.6 v, 10% ? 90% trise2 rise time on gpo2 and gpo3, cload = 50 pf 10 ? 50 ns v dd = 3.0 to 3.6 v, 10% ? 90% trise3 rise time on gpo0 and gpo1, cload = 50 pf 15 ? 80 ns v dd = 1.71 to 3.0v, 10% ? 90% trise2 rise time on gpo2 and gpo3, cload = 50 pf 10 ? 80 ns v dd = 1.71 to 3.0 v, 10% ? 90% trise4 fall time, cload=50 pf all gpo outputs 10 ? 50 ns v dd = 3.0 to 3.6 v, 90% ? 10% tfall2 fall time, cload=50 pf all gpo outputs 10 ? 70 ns v dd = 1.71 to 3.0 v, 90% ? 10% parameter description min typ max unit notes c p parasitic capacitance 5.0 ? (c p +c f )<40 pf c p is the total capacitance seen by the pin when no finger is present. c p is sum of c button , c trace , and capacitance of the vias and c pin c f finger capacitance 0.25 ? (c p +c f )<40 pf c f is the capacitance added by the finger touch c pin capacitive load on pins as input 0.5 1.7 7 pf c mod external modulator capacitor 2 2.2 2.4 nf mandatory for capsense to work rs series resistor between pin and the sensor ?560 616 ? reduces the rf noise
cy8cmbr2044 document number: 001-57451 rev. *e page 22 of 29 ordering information ordering code definitions ordering code package type operating temperature capsense inputs gpos xres pin CY8CMBR2044-24LKXI 16-pin qfn (3 3 0.6 mm) industrial 4 4 yes CY8CMBR2044-24LKXIt 16-pin qfn (3 3 0.6 mm) (tape and reel) industrial 4 4 yes x = blank or t blank = tube; t = tape and reel temperature range: i = industrial pb-free package type: lk = 16-pin qfn speed grade: 24 mhz part number mechanical button replacement technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress i c mbr 2044 - 24 lk cy 8 x x
cy8cmbr2044 document number: 001-57451 rev. *e page 23 of 29 package diagram figure 19. 16-pin chip on lead (3 3 0.6 mm) lg16a/ld16a (sawn) package outline package information 001-09116 *f table 12. thermal impedances by package package typical ? ja [8] 16-pin qfn 32.7 c/w table 13. solder reflow peak temperature package minimum peak temperature [9] maximum peak temperature 16-pin qfn 240 c 260 c notes 8. tj = t a + power x ? ja 9. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with sn -pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications.
cy8cmbr2044 document number: 001-57451 rev. *e page 24 of 29 appendix table 14. device features vs. resistor configuration matrix features comments pin configuration device pin name button auto reset enabled, auto reset period = 5 ms ground / floating arst enabled, auto reset period = 20 ms 5.1 k ? (5%) to ground disabled vdd led on time 0 ms ground delay 20 ms 120 ? (1%) to ground 40 ms 200 ? (1%) to ground 60 ms 280 ? (1%) to ground ???? ???? 1980 ms 7060 ? (1%) to ground 2000 ms 8040 ? (1%) to ground 2000 ms > 8040 ? (1%) to ground 2000 ms vdd / floating toggle on/off / flanking sensor suppression (fss) toggle on/off fss toggle/fss disabled disabled ground / floating enabled disabled 1.5 k ? (5%) to ground disabled enabled 5.1 k ? (5%) to ground enabled enabled vdd
cy8cmbr2044 document number: 001-57451 rev. *e page 25 of 29 table 15. scanrate/sleep pin hardware configuration resistor r (1%) in ohms approximate scanrate (in ms) resistor r (1%) in ohms approximate scanrate (in ms) 60 20 4060 209 185 22 4185 217 310 24 4310 226 435 27 4435 235 560 30 4560 244 685 34 4685 253 810 38 4810 263 935 42 4935 272 1060 46 5060 282 1185 51 5185 291 1310 55 5310 301 1435 61 5435 311 1560 66 5560 321 1685 71 5685 331 1810 77 5810 341 1935 83 5935 352 2060 89 6060 362 2185 96 6185 373 2310 102 6310 383 2435 107 6435 394 2560 115 6560 405 2685 122 6685 416 2810 129 6810 427 2935 137 6935 438 3060 144 7060 449 3185 152 7185 461 3310 159 7310 472 3435 167 7435 484 3560 175 7560 495 3685 183 7685 507 3810 192 7810 519 3935 200 7935 531
cy8cmbr2044 document number: 001-57451 rev. *e page 26 of 29 acronyms document conventions units of measure numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowerc ase 'h' (for example, '14h' or '3ah'). hexadecimal numbers may also be represented by a '0x' prefix, the c coding convention. binary numbers have an appended lowercase 'b' (for example, 01010100b' or '01000011b'). numbers not indicated by an 'h', 'b', or 0x are decimal. acronym description ac alternating current ai analog input aio analog input/output aido analog input/digital output do digital output p power pins c f finger capacitance c p parasitic capacitance cs capsense fss flanking sensor suppression gpo general purpose output lsb least significant bit msb most significant bit pcb printed circuit board por power on reset post power on self test rf radio frequency symbol unit of measure c degree celsius k ? kilohm a microampere s microsecond ma milliampere ms millisecond mv millivolt na nanoampere ? ohm pf picofarad vvolt
cy8cmbr2044 document number: 001-57451 rev. *e page 27 of 29 document history page document title: cy8cmbr2044, four button capsense ? controller document number: 001-57451 rev. ecn no. orig. of change submission date description of change ** 2807997 slan 12/03/2009 new data sheet. *a 2949368 slan 06/10/2010 updated features . updated overview . updated pinout . updated typical circuits (updated schematic 1: 4-button s, 4-leds with auto reset enabled and schematic 2: 3-buttons, 3-leds , 2-outputs to master, and advanced features enabled ). updated device features (added ta b l e 2 , updated hardware configuration (description), updated flanking sensor suppression (fss) (added figure 2 ), updated system diagnostics (added figure 6 , and figure 8 ), added serial debug data ). updated power consumption and device operating modes (updated deep sleep mode (description)). updated layout guidelines and best practices (updated capsense button shapes , updated example pcb layout design with four capsense buttons and four leds ). updated electrical specifications . added ordering code definitions . added units of measure . *b 2975370 slan 07/09/2010 updated features . updated pinout . updated typical circuits . updated device features (updated led on time (updated figure 4 ), updated system diagnostics (updated figure 6 , and figure 8 ), updated serial debug data (description)). updated power consumption and device operating modes (updated deep sleep mode (description)). *c 2996393 slan 07/29/2010 updated features . *d 3036873 arvm 09/23/2010 updated typical circuits (updated schematic 1: 4-button s, 4-leds with auto reset enabled and schematic 2: 3-buttons, 3-leds , 2-outputs to master, and advanced features enabled ). updated layout guidelines and best practices (updated example pcb layout design with four capsense buttons and four leds (updated figure 17 )).
cy8cmbr2044 document number: 001-57451 rev. *e page 28 of 29 *e 3624224 udyg / slan 05/22/2012 updated title to read as ?four button capsense ? controller?. updated features . updated overview . updated pinout (updated table 1 ). updated typical circuits (updated schematic 1: 4-button s, 4-leds with auto reset enabled and schematic 2: 3-buttons, 3-leds , 2-outputs to master, and advanced features enabled ). updated device features (updated ta b l e 2 , updated capsense buttons , updated smartsense auto tuning , updated general purpose outputs , removed hardware configuration, updated toggle on/off , updated flanking sensor suppression (fss) , removed delay off, added led on time , updated button auto reset , renamed failure mode analysis as system diagnostics and updated the same section, renamed debug data as serial debug data and updated the same section, r enamed device operating modes as power consumption and device operating modes ). updated layout guidelines and best practices . updated electrical specifications (updated dc electrical characteristics (updated dc chip level specifications (updated note 6 )), updated dc general purpose i/o specifications ). updated capsense specifications . updated ordering information (removed capsense block column). updated package diagram . added appendix . replaced all instances of sensor with button across the document. updated in new template. document history page (continued) document title: cy8cmbr2044, four button capsense ? controller document number: 001-57451 rev. ecn no. orig. of change submission date description of change
document number: 001-57451 rev. *e revised may 22, 2012 page 29 of 29 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8cmbr2044 ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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